1. Field of the Invention
The present invention relates to a semiconductor device having a lead-on-chip (LOC) structure and a method for manufacturing such a device.
2. Description of the Related Art
As a result of the development of memory devices having a large storage capacity such as dynamic random access memory (DRAM) devices, semiconductor elements of such devices have been dimensionally enlarged and take a remarkably larger space in a memory package than ever. Thus, in recent years package structures having an LOC structure have been proposed in the technological field of designing packages containing semiconductor elements that take a large space in the package.
Meanwhile, as a result of the development of the diffusion technology, semiconductor elements can be made smaller so that semiconductor elements having the same capacity have been increasingly down-sized on almost a year by year basis.
Incidentally, the external dimensions of packages are standardized and hence packages are hardly down-sized in terms of external dimensions even if the semiconductor elements they contain are down-sized. Thus, as the product cycle goes into a stage of maturity, the semiconductor elements of packages tend to occupy a reduced space in the package even if they have an LOC structure.
With the semiconductor element occupying a small space relative to the size of the package, however, the manufacturing yield is reduced, a large warp is created in a package, and a large thermal resistance is created in the package. This will be explained later in detail.